The Nanoscale Thin Film Deposition is a session to present the latest research results related to thin film material processing and device manufacturing for next-generation semiconductor devices. Recently, the importance of the thin film material deposition process with atomic level precision is becoming more and more important because the physical limit of thin films has been reached due to the ultra-miniaturization of semiconductor devices. In addition, based on this, research on thin film processing and device manufacturing with new materials is accelerating. Therefore, the purpose of this symposium is to introduce the latest research results on various materials such as metals and dielectric materials, which will be introduced in the next-generation semiconductor process, and the results applied to devices. In addition, theoretical simulation of deposition reaction and development of chemical precursors are also important fields in this symposium. This symposium brings together a broad community of researchers from a variety of fields including materials science, surface science, inorganic chemistry, condensed matter physics, electrical engineering, and quantum information science to exchange the latest research results and to create a new frontier for thin film deposition researchers.

• Thin film processes toward future nanoscale semiconductor devices
• Chemical and physical based deposition for semiconductor applications
• Atomic layer deposition for nanoscale thin films
• Plasma assisted thin film deposition methods
• Area selective deposition for future semiconductor devices
• New precursor development for CVD and ALD
• Mechanism of nanoscale thin film nucleation and growth
• Application of new materials (oxide, nitride, sulfide and chalcogenide) for future devices
• Simulation for thin film deposition and reactions
• Characterization of nanoscale thin films
• Topics related with semiconducting thin films

The CMP& Cleaning session will focus and discuss the research on novel functional CMP process, CMP slurry, and post cleaning for scaling-down logic and memory devices, being able to perform fast polishing rate, high polishing rate, high polishing rate selectivity, dishing-free, erosion-less, scratch-less, and remaining particle-less for inorganic, organic, and metal film CMPs. In addition, several CMP mechanisms will be reviewed by the applied surface science such as dynamic mechanical and chemical behavior. Beyond conventional CMP abrasives such as colloidal silica and zirconia etc., novel CMP abrasives such as core/shell abrasives and chemical deliverable abrasives will be introduced. Moreover, new indispensable CMP processes will be discussed as the memories and logic devices has scaled down and the following CMP slurry and post-cleaning will be debated. Furthermore, as the design rule of DRAM, 3D NAND flash memory, logic device has scaled down less than 10 nm, 256 floors, and 2 nm, the presence of a physical limit or not will be discussed for a CMP application.

• CMP process, CMP slurry, post-cleaning process for STI, ILD, poly silicon, nitride, tungsten, copper, amorphous carbon, and GeSbTe film planarization.
• Super-fine(abrasive dimeter: < 5 nm) ceria CMP slurry, related post cleaning, and CMP process application.
• Extremely high surface topography(i.e., > 1 μm) CMP slurry and process.
• Self-stop CMP slurry and process.
• Amorphous carbon and spin-on-glass CMP slurry and process.
• Core/shell(inorganic/organic & organic/organic) abrasive based CMP slurry and CMP performance.
• Chemical deliverable abrasive based CMP slurry and CMP performance.
• Eco-friendly post cleaning chemical and process.
• Structure induced stress simulation and stress induced CMP defects.

As the device integration is increased continuously, the critical dimension of semiconductor device has decreased to a few nanometers and the device structure is changing from two dimensional (2D) structures to three dimensional (3D) structures. Due to the complexity of the device fabrication and the use of various materials for the semiconductor devices, the etching technology has become one of the most difficult technologies for next generation semiconductor device fabrication requiring low damage etching, highly selective etching, high aspect ratio etching, etc. on 2D and 3D structured materials. In this session, the advanced etch technologies such as ALE, cyclic etching, pulsed plasma etching, etching with low GWP materials, etc. which are required for the next generation semiconductor device fabrication will be presented. The researchers and engineers working in the etching of the semiconductor and display materials are welcome to this session, and encouraged to attend and present their works in this session.

• Cryogenic etching
• Atomic layer etching/Cyclic etching/Atomic layer cleaning
• Etching technology for nonvolatile materials
• Pulsed plasma etching
• Etching technology for low global warming potentials
• Highly selective isotropic etching
• Etching/Modification of 2D materials
• HARC etching
• New plasma etching technologies
• Plasma sources for next generation plasma etching
• Etching for various materials and for various applications
• Etching technology for displays
• Simulation techniques for etching
• Etc.

Lithography continues to be challenged to extend into ever-shrinking generations, yet remain manufacturable and cost effective. State-of-the-art processes continue with immersion lithography and multiple patterning, while EUV lithography moves closer toward production readiness. At the same time, the lithography community aggressively pursues alternative patterning approaches and complementary solutions. Success calls for unique interdisciplinary interactions and coordinated efforts between lithographers, layout designers, materials scientists, and metrology/process control engineers to enable cost-efficient patterning solutions.
A full spectrum of lithography and patterning topics are encompassed by this symposium. Participants come from a broad array of backgrounds to share and learn about state-of-the-art lithographic tools, resists, metrology, materials, design, process integration, and novel new approaches. Through provocative discussions and seminars, the symposium also probes current issues being faced as we extend current methods, move toward alternative approaches, and identify new ways to complement one technology with another.

• EUV Lithography _ EUV scanner, EUV tool, EUV mask, EUV OPC, EUV Patterning material
• Patterning Materials_ EUV resist, photoresists for optical lithography, materials for alternative lithography, photopatternable functional materials
• Nano Fabrication for next generation optical devices_ Nanoprinting for optical metasurfaces, printable nanolasers
• Alternative Lithography_ 3D Patterning, Imprinting, Self-assemble, non-conventional lithography
• Layout optimization & Computational Lithography_ DTCO(design technology co-optimization), DFM(design for manufacturing), SMO(source mask optimization)
• Advanced Metrology and Inspection_ optical inspection, interference microscopy, advanced process control, overlay metrology, computational metrology
• Applications and Related Emerging Topics

The importance of low power and multi-functionalities is increasing in future semiconductors, which require alternativ materials, processes, devices and systems. In addition to continuous device scaling driven by advanced lithography technology, heterogeneous integration including 3D IC, system-in-package, and monolithic 3D (M3D) has garnered much interest. In this regard, the heterogeneous integration packaging session will focus on advanced packaging materials, processes and integrations for mobile, HPC, automotive, 5G, health and chiplets.

• Advanced packaging for heterogeneous integration
• 2.5D and 3D packaging technology
• Fan-out and Fan-In technology
• Hybrid and direct bonding for 3D integration
• Thermal/mechanical simulation & characterization
• Advanced device and system using heterogeneous integration
• Monolithic 3D integration
• Topics related with heterogeneous integration

The nano-analysis is for a symposium to present the latest research results related to chemical, physical, and electrical analysis on nano-scale particles, defects, and contaminationsaroused in theprocess for manufacturing next-generation semiconductor devices. Recently, the importance of the nano-analysis with atomic level precision has been incresing more and more because the dimensions of semiconductor devices have been scaled down to a few nano-scale. In addition, this topic is covered with metrology, diagnosis, and inspection researches on nano-scalefilms and devices. Therefore, the purpose of this symposium is to introduce the latest research results on various nano-scale analysisonparticles, defects, and contaminations, which influence directly on the process uniformity and device yieldof nano-scale semiconductor device during process.

• Topics related with physical and chemical analysis of nano-scale particles and defects
• Topics related with chemical analysis of contaminationson organic and inorganic materials
• Topics related with MI in the semiconductor process
• Topics related with diagnosis for controlsemiconductor process

The Electronic Materials, Devices and Related technology session will focus and open discuss on other topics not include session 01-session 06 but all electronic materials, devices and software, and semiconductor related topics. This session included the same scopes to the fall conference of KSDT 2023, therefor there is no limitations. After reviewing process, the program committee will allocate their research results to the most close topic session.

• Design of future nanoscale semiconductor devices
• Synthesis of nanomaterials and characterizations for applications
• Oxide and nitride based semiconductors and their applications
• Fundamentals and applications of Display technology
• Optoelectronics and various sensors
• Power devices and applications
• Semiconductor circuits design related topics
• Development of PIM related topics
• Application of novel materials for future electronic devices
• AI related hardware and software
• Topics related with semiconducting physics and technology

Jinsub Park (Hanyang Univ., Korea)